A non-volatile memory device may retain its stored data even when its power supply is interrupted. Types of non-volatile memory devices include PROM (Programmable Read Only Memory), EPROM (Erasable PROM), EEPROM (Electrically Erasable PROM), and Flash Memory. These non-volatile memory devices may be further classified into two groups: a NAND-type flash memory and a NOR-type flash memory. A NOR-type flash memory device may be used as a code storage memory device in applications of mobile cellular phones requiring fast data processing.
A NOR-type flash memory device may have a memory cell including source/drain regions doped with N+ impurities formed on a P-type semiconductor substrate with a channel region therebetween. The flash memory cell may also have a floating gate and a control gate. The floating gate may be formed on the channel region with a relatively thin insulating layer of 100 Å (Angstroms) or less between the floating gate and the channel region. The control gate may be formed on the floating gate with an insulating layer between the floating gate and the control gate. A bias voltage may be applied to a source, a drain, a gate, and a substrate of a memory cell during programming, erasing, and/or reading. To read data from the programmed cell, for example, a voltage of about 1V (volt) is applied to the drain, a power source voltage (e.g., about 4.5V) is applied to the control gate, a voltage of 0V is applied to the source, and a voltage of 0V is applied to the substrate.
The NOR-type flash memory device may provide a relatively large memory capacity in a relatively small area. To improve memory capacity, integration densities may need to be improved. Industry demands for more efficient integration density in flash memories and for expanded memory capacity have led to the development of multi-bit (also known as multi-level, multi-state, and/or multiple bit) technologies. A memory cell used to store multi-bit data may be referred to as a MLC (Multilevel Cell) or a multi-bit cell. For example, a programmed memory cell may store one of four data states, (i.e., “00”, “01”, “10”, and “11”) according to a distribution of a threshold voltage. The four states may be classified according to differences in the current flowing through the memory cell during read operations.
To sense multi-bit data stored in the memory cell, sense amplification may be used. Sense amplification is used to sense and amplify a difference of a current flowing through the memory cell and a reference current, and to thereby sense the multi-bit data stored in the memory cell. For this, a multiplicity of reference memory cells may be required. In addition, sense amplification may require circuits capable of providing different currents.
A conventional sense amplification may provide different current paths for different reference currents. A sense amplification, for example, may use three NMOS transistors to sense 2-bit data. The NMOS transistors may be connected in parallel with respect to each other to provide different current paths.
It may be difficult, however, to provide that the current paths have a same characteristic (e.g., the same threshold voltage). A sensing margin may be reduced due to a mismatch between different current paths. In a conventional flash memory device, for example, a NMOS transistor used to sense data during read operations may be different from a NMOS transistor used to sense data during program verify operations. In this case, a sensing margin may be reduced because a current path is changed despite sensing data of a same state. As a result, exact sensing may be difficult to perform, and sensing results may vary.
Additionally, there may be a disadvantage of a long program verify time because the program verify operation of the conventional NOR-type flash memory device is performed via verify steps twice irrespective of the memory cell state. When the “01” state is program-verified, for example, the “01” state as well as the “00” state may also be program-verified. When the “10” state is program-verified, the “01” state may be program-verified, and then the “10” state may be program-verified again. Performing the program verify step twice may undesirably increase a program verify time.